toshiba toshiba TC86R4400 mips risc high performance microprocessor product brief toshiba america electronic components, inc . 1 toshiba is the leading silicon vendor licensed to develop, manu- facture and sell mips a reduced instruction set computing (risc)-based products. toshiba?s r4400-based systems will run a choice of advanced operating systems, such as unix a and windows nt ? from microsoft corporation. toshiba is the key supplier of mips reduced instruction set computing (risc) technology for the computer system and embedded control markets. from the introduction of the r2000 ? , toshiba has been a foundry for mips risc-based products. since then, the r3000, r4000 and r4400 processors have been gaining wide acceptance and have been designed into a variety of products by industry-leading companies. in 1991, toshiba delivered one of the trst r4000 compo- nents, displaying its strength in advanced process technology applied to high-end microprocessors. with a leading combination of highest overall performance, 64-bit architecture and design ?exibility, toshiba?s r4400 establishes the standard for risc microprocessors through the end of this decade. r4400 performance the single-chip r4400 delivers the high performance necessary for a wide range of applications while maintaining full software compatibility with previous generations of mips microproces- sors. its scalable performance makes it possible to design the r4400 into applications ranging from embedded controllers, such as those in satellites and telephone switches, to computers rang- ing from laptops to mainframe-class servers. in designing the r4400, the basic components of the central cpu subsystem, including integer processor, ?oating point co-processor, memory management unit and primary cache, were integrated onto a sin- gle chip. in addition, the r4400 includes full multiprocessing capabilities, superpipelining, and control and management facili- ties for external secondary cache. the r4400 is offered in two variants tailored for multiple price/performance points: the r4400sc supports high-performance uniprocessor designs with secondary cache the r4400mc is the full multiprocessing version of the prod- uct and supports both secondary cache and cache coherence mechanisms necessary for synchronizing multiple processors the r4400 family provides a balanced mix in integer and ?oating point performance. through superpipelining, risc opti- mization techniques and on-chip integration, high integer perfor- mance is achieved for applications such as databases, graphics, spreadsheets and word processing. superpipelining increases throughput by putting more instructions into the pipeline at the same time. risc optimization techniques streamline processing operations by minimizing interruptions to the steady progress of the pipeline. in addition, on-chip integration takes more function- ality off the board and puts it directly onto the processor to shorten paths and reduce lengthy accesses to main memory. in the r4400 design, superpipelining requires less circuitry than other multiple-instruction issue techniques, so it leaves more room on the chip for other functions. further, superpipelining provides greater integer processing than most other techniques whose benetts are contned mainly to ?oating-point operations. this results in higher overall performance from integer and ?oat- ing-point units, a desirable characteristic in a microprocessor that is to have broad-based acceptance and applications. the r4400 takes advantage of optimization techniques built into the mips compiler software to run applications faster than other risc processors at similar or higher clock speeds. with risc, the microprocessor design is streamlined by eliminating less frequently used instructions and circuitry, shifting the bal- ance of computing from hardware to compiler software. compil- ers offered by mips have been simultaneously developed and integrated with the r4400 from the start to deliver maximum per- formance. table 1. TC86R4400sc/mc options internal frequency external frequency voltage temperature internal cache package (pga) 150 mhz 75 mhz 3.3v 70 c 16ki + 16kd 447-pin 175 mhz 87 mhz 3.3v 70 c 16ki + 16 kd 447-pin 200 mhz 100 mhz 3.3v 70 c 16ki + 16 kd 447-pin 200 mhz 100 mhz 3.3v 85 c 16ki + 16 kd 447-pin 200 mhz 100 mhz 3.45v 70 c 16ki + 16 kd 447-pin 250 mhz 125 mhz 3.45v 70 c 16ki + 16 kd 447-pin
TC86R4400 mips risc microprocessor 2 toshiba america electronic components, inc . r4400sc micr opr ocessor t oshiba? s r4400sc 64-bit microprocessor and an advanced operating system, like w indows nt ?, gives the designer the ability to address new expectations in the mainstream system and high-end server/workstation market at unbeatable price/ performance points. r4400sc-based systems can run a choice of advanced operating systems, such as w indows nt and unix a which protect end user software investments while also providing an open software environment, are two important achievements for t oshiba in meeting the mainstream and high-end pc market needs. the r4400sc operates from 150mhz (input clock 75 mhz) to 250mhz (input clock 125mhz), and can sustain performance in excess of 175specint92. r4400sc overview t oshiba? s r4400sc is a highly integrated, single-chip risc microprocessor designed for high-performance uniprocessor sys- tems with secondary cache support. the r4400sc provides com- plete application software compatibility with the mips r2000, r3000, r4000, and r8000 processors. high integer performance, as well as ? oating-point performance, has been achieved through a number of techniques such as superpipelining, on-chip data and instruction caches, a pipelined ? oating point unit, support for two level cache memory and a high-performance on-chip tlb. the r4400sc provides a compatible, timely and necessary path from 32-bit to true 64-bit computing for users and software developers. r4400sc featur es true 64-bit microprocessor with 64-bit integer and floating- point operations, registers and virtual addresses fully compatible with earlier 32-bit mips microprocessor. dual instruction issue with no restrictions on the type of instruction issued on-chip memory management unit (mmu) containing a fully associative tlb whose entries have a variable page size rang- ing from 4kbyte to 16mbyte on-chip ansi/ieee-754 standard floating-point unit with precise exceptions 32 doubleword (64-bit) general-purpose registers and 32 doubleword floating-point registers 36-bit physical address accessing 64gb of physical memory built in primary direct mapped caches with parity protection: e 16kb instruction cache e 16kb data cache e buf fered write back with cont gurable 4 or 8 word line size r4400sc also has built-in direct mapped secondary cache support: e the secondary cache can range from 128kbytes to 4mbytes e 128-bit interface to minimize cache miss latency e t iming ? exibility for 128-bit secondary cache interface e ecc protection 64-bit system interface to allow speed matching of logic and memory components dynamically configurable big-endian or little-endian byte ordering in order to achieve the high performance required in a third generation risc design, the TC86R4400sc exploits instruction- level parallelism using a superpipelined micro-instruction. the TC86R4400sc implements an 8-stage superpipeline which places no restrictions on instruction issue. any two instructions can be issued each cycle under normal circumstances. since the superpipeline places no restrictions on the order of instruction issue, the full benet t of the TC86R4400sc can be realized by existing application programs without any need for recompila- tion. the internal pipeline of the TC86R4400sc operates at fre- quency from 150mhz to 200mhz, which is twice the external clock frequency . r4400mc micr opr ocessor TC86R4400mc-based multiprocessor computer systems can run a choice of advanced operating systems, such as w indows nt , unix and univel. protecting the end user soft- ware investments and also providing an open software environ- ment are two important achievements in meeting the high-end market needs. the TC86R4400mc operates at frequencies from 150mhz internal (external clock 75mhz) to 250mhz internal (125mhz external), and can sustain performance in excess of 175specint92. r4400mc overview t oshiba r4400mc is a highly integrated, single-chip risc microprocessor designed for high-performance multiprocessing systems. the r4400mc provides complete application-software compatibility with the mips r2000, r3000, r4400 and r8000 processors. high integer performance, as well as ? oating-point performance, has been achieved through a number of techniques such as superpipelining, on-chip data and instruction caches, a pipelined ? oating point unit, support for two level cache memory and a high-performance on-chip tlb. the r4400mc provides a compatible, timely and necessary path from 32-bit to true 64-bit computing for users and software developers.
r4400sc/mc multiprocessor toshiba america electronic components, inc . 3 r4400mc featur es true 64-bit microprocessor with 64-bit integer and floating- point operations, registers and virtual addresses fully compatible with earlier 32-bit mips microprocessors dual instruction issue with no restrictions on the type of instruction issued built-in support for multiprocessing on-chip memory management unit (mmu) containing a fully associative tlb whose entries have a variable page size rang- ing from 4kb to 16mb on-chip ansi/ieee-754 standard floating-point unit with precise exceptions 32 doubleword (64-bit) general-purpose registers and 32 doubleword floating-point registers 36-bit physical address accessing 64gb of physical memory built-in primary direct mapped caches with parity protection: e 16kb instruction cache e 16kb data cache e buf fered write back with cont gurable 4 or 8 word line size built-in direct mapped secondary cache support: e the secondary cache can range from 128kb to 4mb e 128-bit interface to minimize cache miss latency e t iming ? exibility for 128-bit secondary cache interface e 64-bit system interface to allow speed matching of logic and memory components with multiprocessing support e ecc protection dynamically configurable big-endian or little-endian byte ordering figur e 1. r4400 block diagram figur e 2. r4400mc system block diagram external secondary cache rams 128 data 64 data secondary cache bus data, tag, addr, control 64-bit dbus 64-bit ibus system bus integer unit memory management unit system coprocessor 0 (cp0) floating point unit item coprocessor 1 (cp1) 16k primary data cache 16k primary instruction cache decode tag decode tag fp register file fp pipeline/bypass fp status register fp multiply fp divide fp add, convert, square root primary cache control system secondary cache control pipeline control alu exception/control registers translation lookside buffer (96 entries, software managed) memory management unit registers address unit pc incrementer register file integer multiply/divide load aligner store driver
TC86R4400 mips risc microprocessor toshiba ? 1995 t oshiba america electronic components, inc. t oshiba products described in this document are not authorized for use as critical components in life support systems without th e written consent of the appropriate of t cer of t oshiba america, inc. life support systems are either systems intended for sur gical implant in the body or systems which sustain life. a critical component is any component of a life support system whose failure to perform may cause a malfunction or failure of the life support system, or may af fect its safety or ef fectiveness. specit cations and information herein are subject to change without notice. this technical data may be controlled under u.s. export administration regulations and may be subject to the approval of the u.s. department of commerce prior to export. any export or re-export, directly or indirectly , in contravention of the u.s. export administration regulations is strictly prohibited. brand names and product names mentioned herein may be trademarks or registered trademarks of their respective companies. t aec regional sales offices southwest irvine, ca tel: (714) 453-0224 f ax: (714) 453-0125 nor thwest portland, or tel: (503) 629-0818 f ax: (503) 629-0827 san jose, ca tel: (408) 456-8900 f ax: (408) 456-8910 central dallas, tx tel: (214) 480-0470 f ax: (214) 235-41 14 chicago, il tel: (708) 945-1500 f ax: (708) 945-1044 nor theast boston, ma tel: (617) 224-0074 f ax: (617) 224-1096 edison, nj tel: (908) 248-8070 f ax: (908) 248-8030 southeast atlanta, ga tel: (770) 368-0203 f ax: (770) 368-0075 figur e 3. r4400sc system block diagram multiprocessor bus interface component interface component interface component system memory i/o controller i/o controller r4400mc r4400mc l2 cache l2 cache 64 64 64 128 128 64 64 128 64 64 i/o bus i/o bus r4400sc sram dram dram memory & i/o controller data data control address 128-bit data tag, addrs control (64 + 8) address/data command bus (9-bits) scsi enet system i/o bus buffer buffer rsc-1 156/8-95
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